Commit d2843fbf80 for qemu.org

commit d2843fbf80260e4346c856819e8cea11768c9d0e
Merge: 99e54ab5e7 b23a62773a
Author: Peter Maydell <peter.maydell@linaro.org>
Date:   Fri Sep 4 09:43:27 2026 +0100

    Merge tag 'pull-riscv-to-apply-20260904' of https://github.com/alistair23/qemu into staging

    RISC-V PR for 11.2

    * Add initial sdext support
    * Make RISCVBootInfo const where possible
    * Use hwaddr for virt IMSIC device tree address
    * Avoid unnecessary removal of test scratch files
    * Document Atlantis QEMU-only I2C device tree nodes
    * Make s-mode IMSIC stride explicit
    * Correct dasm for cbo and lq
    * Add tests for rv128 [ms]status
    * Code duplication work in preperation for riscv-server-ref
    * Fix user option hash table leaks
    * Preserve vl on element-zero fault
    * Prevent abrupt abortion on unassigned value write to tdata
    * Socify Atlantis

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    * tag 'pull-riscv-to-apply-20260904' of https://github.com/alistair23/qemu: (47 commits)
      hw/riscv/atlantis: Map the SoC through a memory container
      hw/riscv/atlantis: Extract an Atlantis SoC device
      hw/riscv: Add property to hart array to allow private memory
      hw/riscv/atlantis: Make TTAtlantisState own memory containers
      hw/riscv/atlantis: Decouple RAM size from MachineState
      hw/riscv/atlantis: Use local reference for system memory
      hw/riscv/atlantis: Rework device tree creation
      hw/riscv/atlantis: Rename hart array 'soc' to 'cpus'
      hw/riscv/atlantis: Remove unused fdt_size
      hw/riscv/atlantis: Make UART unimp region a SoC device
      hw/riscv/cps: Map interrupt controllers in SoC container
      hw/intc/sifive_plic: Take a MemoryRegion for the created device
      hw/intc/riscv_aplic: Take a MemoryRegion for the created device
      hw/intc/riscv_imsic: Take a MemoryRegion for the created device
      hw/intc/riscv_aclint: Take a MemoryRegion for the created devices
      hw/riscv/aia: Take a MemoryRegion for the created devices
      target/riscv: prevent abrupt abortion on unassigned value write to tdata
      target/riscv: preserve vl on element-zero fault
      target/riscv/tcg: fix user option hash table leaks
      hw/riscv/riscv-iommu-sys.c, virt.c: add riscv_create_iommu_sys()
      ...

    Signed-off-by: Peter Maydell <peter.maydell@linaro.org>