Commit d4151cf267 for qemu.org

commit d4151cf2675124e26b3383ae06f7352a23f17399
Author: Richard Henderson <richard.henderson@linaro.org>
Date:   Wed Aug 12 15:31:28 2026 -0700

    disas/riscv: Fix rv32 encoding of zext.h

    For rv64, pack with rs2 = 0 does not encode zext.h.

    Cc: qemu-stable@nongnu.org
    Fixes: 02c1b569a15 ("disas/riscv: Add Zb[abcs] instructions")
    Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
    Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
    Message-ID: <20260812223142.349142-39-richard.henderson@linaro.org>
    Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

diff --git a/disas/riscv.c b/disas/riscv.c
index e650ad7688..5624e7f60a 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -3506,9 +3506,10 @@ static const rv_opcode_data *decode_inst_opcode(rv_decode *dec, rv_isa isa)
             case 14: op = rv_op_rem; break;
             case 15: op = rv_op_remu; break;
             case 36:
-                switch ((inst >> 20) & 0b11111) {
-                case 0: op = rv_op_zext_h; break;
-                default: op = rv_op_pack; break;
+                if (isa == rv32 && !((inst >> 20) & 0b11111)) {
+                    op = rv_op_zext_h;
+                } else {
+                    op = rv_op_pack;
                 }
                 break;
             case 39: op = rv_op_packh; break;