Commit d610e55c83 for qemu.org

commit d610e55c8390a8bfd15d0a4f1521d7fc46e4e0b7
Author: Richard Henderson <richard.henderson@linaro.org>
Date:   Wed Aug 12 15:31:29 2026 -0700

    disas/riscv: Fix isa decoding of rev8

    The encoding of rev8 is different for rv32 and rv64.

    Cc: qemu-stable@nongnu.org
    Fixes: 02c1b569a15 ("disas/riscv: Add Zb[abcs] instructions")
    Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
    Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
    Message-ID: <20260812223142.349142-40-richard.henderson@linaro.org>
    Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

diff --git a/disas/riscv.c b/disas/riscv.c
index 5624e7f60a..787340e811 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -3292,8 +3292,16 @@ static const rv_opcode_data *decode_inst_opcode(rv_decode *dec, rv_isa isa)
                 case 0b01100: op = rv_op_rori; break;
                 case 0b01101:
                     switch ((inst >> 20) & 0b1111111) {
-                    case 0b0011000: op = rv_op_rev8; break;
-                    case 0b0111000: op = rv_op_rev8; break;
+                    case 0b0011000:
+                        if (isa == rv32) {
+                            op = rv_op_rev8;
+                        }
+                        break;
+                    case 0b0111000:
+                        if (isa == rv64) {
+                            op = rv_op_rev8;
+                        }
+                        break;
                     case 0b0000111: op = rv_op_brev8; break;
                     }
                     break;