Commit d6c782fdb9 for qemu.org

commit d6c782fdb9f0c98ccf8e54d70165420e58e3c767
Author: Charlie Jenkins <thecharlesjenkins@gmail.com>
Date:   Thu Jun 25 22:12:02 2026 -0700

    target/riscv: Report QEMU CPU archid as 42

    When a non-vendor CPU is used, report the archid as 42 which has been
    allocated for QEMU in the riscv isa manual [1]. This can help software
    check if it is running in QEMU.

    [1] https://github.com/riscv/riscv-isa-manual/blob/main/marchid.md

    Signed-off-by: Charlie Jenkins <thecharlesjenkins@gmail.com>
    Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
    Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
    Message-ID: <20260625-marchid-v2-1-3821c351028b@gmail.com>
    Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index bff3ed5de1..de94f5d57e 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -47,6 +47,13 @@
 static const char riscv_single_letter_exts[] = "IEMAFDQCBPVH";
 const uint32_t misa_bits[] = {RVI, RVE, RVM, RVA, RVF, RVD, RVV,
                               RVC, RVS, RVU, RVH, RVG, RVB, 0};
+#define RISCV_CPU_MVENDORID 0
+#define RISCV_CPU_MIMPID 0
+/*
+ * marchid allocated for qemu:
+ * https://github.com/riscv/riscv-isa-manual/blob/main/marchid.md
+ */
+#define RISCV_CPU_MARCHID 42

 /*
  * From vector_helper.c
@@ -1204,6 +1211,10 @@ static void riscv_cpu_init(Object *obj)
         mcc->def->profile->enabled = true;
     }

+    cpu->cfg.mvendorid = RISCV_CPU_MVENDORID;
+    cpu->cfg.marchid = RISCV_CPU_MARCHID;
+    cpu->cfg.mimpid = RISCV_CPU_MIMPID;
+
     env->misa_ext_mask = env->misa_ext = mcc->def->misa_ext;
     riscv_cpu_cfg_merge(&cpu->cfg, &mcc->def->cfg);