Commit d7a6df755b for qemu.org

commit d7a6df755b97c959925cad5439e2c688d08b268f
Author: Brian Cain <brian.cain@oss.qualcomm.com>
Date:   Mon Jul 13 18:09:51 2026 -0700

    target/hexagon: handle misaligned load/store cause codes in cpu_loop

    Add a linux-user cpu_loop handler for HEX_CAUSE_MISALIGNED_LOAD and
    HEX_CAUSE_MISALIGNED_STORE, raising SIGBUS for consistency with
    hexswi.c's sysemu handling, even though linux-user's own alignment
    check in accel/tcg/user-exec.c currently raises SIGBUS before
    Hexagon's cause-code machinery is reached.

    Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
    Reviewed-by: Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm.com>
    Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>

diff --git a/linux-user/hexagon/cpu_loop.c b/linux-user/hexagon/cpu_loop.c
index 0958c51fbb..d7f73439db 100644
--- a/linux-user/hexagon/cpu_loop.c
+++ b/linux-user/hexagon/cpu_loop.c
@@ -76,6 +76,11 @@ void cpu_loop(CPUHexagonState *env)
             force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPC,
                     env->gpr[HEX_REG_PC]);
             break;
+            case HEX_CAUSE_MISALIGNED_LOAD:
+            case HEX_CAUSE_MISALIGNED_STORE:
+            force_sig_fault(TARGET_SIGBUS, TARGET_BUS_ADRALN,
+                    env->gpr[HEX_REG_PC]);
+            break;
             default:
                 EXCP_DUMP(env, "\nqemu: unhandled CPU precise exception "
                     "cause code 0x%x - aborting\n",