Commit d9cb9dcf5b for qemu.org
commit d9cb9dcf5b40ed742abec20c57b1bc0227bc2690
Author: Brian Cain <brian.cain@oss.qualcomm.com>
Date: Tue Sep 8 21:01:35 2026 -0700
target/hexagon: widen v81 CPU masks
Reviewed-by: Marco Liebel <marco.liebel@oss.qualcomm.com>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c
index 9f53fcb6b9..4e9a9670d5 100644
--- a/target/hexagon/genptr.c
+++ b/target/hexagon/genptr.c
@@ -269,14 +269,18 @@ static const uint32_t sreg_immut_masks[NUM_SREGS] = {
[HEX_SREG_SSR] = 0x00008000,
[HEX_SREG_CCR] = 0x10e0ff24,
[HEX_SREG_HTID] = IMMUTABLE,
- [HEX_SREG_IMASK] = 0xffff0000,
[HEX_SREG_GEVB] = 0x000000ff,
};
G_GNUC_UNUSED
static void gen_log_sreg_write(DisasContext *ctx, int rnum, TCGv_i32 val)
{
- const uint32_t reg_mask = sreg_immut_masks[rnum];
+ uint32_t reg_mask = sreg_immut_masks[rnum];
+
+ if (rnum == HEX_SREG_IMASK &&
+ ctx->hex_def->hex_version < HEX_VER_V81) {
+ reg_mask = 0xffff0000;
+ }
if (reg_mask != IMMUTABLE) {
if (rnum < HEX_SREG_GLB_START) {
diff --git a/target/hexagon/reg_fields_def.h.inc b/target/hexagon/reg_fields_def.h.inc
index 29497fbcc4..a6b17011d8 100644
--- a/target/hexagon/reg_fields_def.h.inc
+++ b/target/hexagon/reg_fields_def.h.inc
@@ -44,7 +44,7 @@ DEF_REG_FIELD(IPENDAD_IAD, 16, 16)
DEF_REG_FIELD(IPENDAD_IPEND, 0, 16)
DEF_REG_FIELD(SCHEDCFG_EN, 8, 1)
-DEF_REG_FIELD(SCHEDCFG_INTNO, 0, 4)
+DEF_REG_FIELD(SCHEDCFG_INTNO, 0, 5)
DEF_REG_FIELD(BESTWAIT_PRIO, 0, 9)
@@ -109,14 +109,13 @@ DEF_REG_FIELD(SSR_SS, 30, 1)
DEF_REG_FIELD(SSR_XE, 31, 1)
/* misc registers */
-DEF_REG_FIELD(IMASK_MASK, 0, 16)
+DEF_REG_FIELD(IMASK_MASK, 0, 32)
DEF_REG_FIELD(STID_PRIO, 16, 8)
DEF_REG_FIELD(STID_STID, 0, 8)
-/* MODECTL fields */
-DEF_REG_FIELD(MODECTL_E, 0, 8)
-DEF_REG_FIELD(MODECTL_W, 16, 8)
+DEF_REG_FIELD(MODECTL_E, 0, 16)
+DEF_REG_FIELD(MODECTL_W, 16, 16)
DEF_REG_FIELD(CCR_L1ICP, 0, 2)
DEF_REG_FIELD(CCR_L1DCP, 3, 2)