Commit db13fe80ef for qemu.org

commit db13fe80ef455f9e2be60c1bdc6be67a6b82d24f
Author: Xiaoyao Li <xiaoyao.li@intel.com>
Date:   Tue May 12 16:21:08 2026 +0800

    i386/tdx: Add CPUID_24_0_EBX_AVX10_VL_MASK as supported

    AVX10 depends on CPUID_24_0_EBX_AVX10_VL_MASK as defined in
    feature_dependencies[]. Currently CPUID_24_0_EBX_AVX10_VL_MASK is always
    not supported for TDX, so AVX10 cannot be exposed to TD guest.

    The TDX virtualization type of these bits is "XFAM & CPUID_Enabled &
    Native": their value is determined by XFAM[5:7], the AVX10 CPUID bit,
    and the native hardware value.

    For simplicity, add CPUID_24_0_EBX_AVX10_VL_MASK to tdx_xfam_deps[]
    under the AVX512/XFAM dependency, without separately checking the AVX10
    bit. It's safe because any invalid combination supplied by the user will
    be caught by tdx_check_features().

    Signed-off-by: Xiaoyao Li <xiaoyao.li@intel.com>
    Tested-by: Chenyi Qiang <chenyi.qiang@intel.com>
    Link: https://lore.kernel.org/r/20260512082108.621596-4-xiaoyao.li@intel.com
    Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

diff --git a/target/i386/kvm/tdx.c b/target/i386/kvm/tdx.c
index e3c5eb9984..f882578c70 100644
--- a/target/i386/kvm/tdx.c
+++ b/target/i386/kvm/tdx.c
@@ -571,6 +571,9 @@ typedef struct TdxXFAMDep {
  * - AMX alias bits, their type is "CPUID_Enabled & Native" which means their
  * value is determined by the CPUID bit they are aliased to.
  *
+ * - AVX10_VL_MASK, their type is "XFAM & CPUID_Enabled & Native" which means
+ * their value is determined by both the corresponding XFAM bit and CPUID bit.
+ *
  * For simplicity, relax the dependency to related XFAM bit.
  * tdx_check_features() will eventually catch the unsupported configurations.
  */
@@ -579,6 +582,7 @@ TdxXFAMDep tdx_xfam_deps[] = {
     { XSTATE_YMM_BIT,       { FEAT_7_0_EBX, CPUID_7_0_EBX_AVX2 } },
     { XSTATE_OPMASK_BIT,    { FEAT_7_0_ECX, CPUID_7_0_ECX_AVX512_VBMI } },
     { XSTATE_OPMASK_BIT,    { FEAT_7_0_EDX, CPUID_7_0_EDX_AVX512_FP16 } },
+    { XSTATE_OPMASK_BIT,    { FEAT_24_0_EBX, CPUID_24_0_EBX_AVX10_VL_MASK } },
     { XSTATE_PT_BIT,        { FEAT_7_0_EBX, CPUID_7_0_EBX_INTEL_PT } },
     { XSTATE_PKRU_BIT,      { FEAT_7_0_ECX, CPUID_7_0_ECX_PKU } },
     { XSTATE_CET_U_BIT,     { FEAT_7_0_ECX, CPUID_7_0_ECX_CET_SHSTK } },