Commit dbd7359232 for qemu.org

commit dbd7359232a94d8f8e68b57ef54de73cbce7f02d
Author: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Date:   Wed Aug 19 01:52:37 2026 +0200

    target/hexagon: Constify CPUHexagonState in hexagon_thread_is_enabled()

    @env argument is accessed without modification in
    hexagon_thread_is_enabled(), qualify it as const.

    Signed-off-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
    Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
    Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>
    Message-Id: <20260901095229.72018-9-philmd@oss.qualcomm.com>

diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index 0530ec3ca9..4a7b76e3bc 100644
--- a/target/hexagon/cpu.c
+++ b/target/hexagon/cpu.c
@@ -346,9 +346,9 @@ static void hexagon_cpu_synchronize_from_tb(CPUState *cs,
 }

 #ifndef CONFIG_USER_ONLY
-bool hexagon_thread_is_enabled(CPUHexagonState *env)
+bool hexagon_thread_is_enabled(const CPUHexagonState *env)
 {
-    HexagonCPU *cpu = env_archcpu(env);
+    const HexagonCPU *cpu = env_archcpu(env);
     uint32_t modectl;
     uint32_t thread_enabled_mask;
     bool E_bit;
diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
index ed5671abe5..8a4a81dc26 100644
--- a/target/hexagon/cpu.h
+++ b/target/hexagon/cpu.h
@@ -217,7 +217,7 @@ G_NORETURN void hexagon_raise_exception_err(CPUHexagonState *env,
  * @return true if the @a thread_env hardware thread is
  * not stopped.
  */
-bool hexagon_thread_is_enabled(CPUHexagonState *thread_env);
+bool hexagon_thread_is_enabled(const CPUHexagonState *thread_env);
 uint32_t hexagon_greg_read(CPUHexagonState *env, uint32_t reg);
 void hexagon_cpu_soft_reset(CPUHexagonState *env);
 #endif
diff --git a/target/hexagon/cpu_helper.c b/target/hexagon/cpu_helper.c
index 17d6b4eb2b..9ce260d744 100644
--- a/target/hexagon/cpu_helper.c
+++ b/target/hexagon/cpu_helper.c
@@ -316,9 +316,9 @@ void hexagon_ssr_set_cause(CPUHexagonState *env, uint32_t cause)
 }


-int get_exe_mode(CPUHexagonState *env)
+int get_exe_mode(const CPUHexagonState *env)
 {
-    HexagonCPU *cpu;
+    const HexagonCPU *cpu;
     uint32_t modectl, thread_enabled_mask, thread_wait_mask;
     uint32_t isdbst, debugmode;
     bool E_bit, W_bit, D_bit;
@@ -488,7 +488,7 @@ static int sys_in_user_mode_ssr(uint32_t ssr)
     return 0;
 }

-int get_cpu_mode(CPUHexagonState *env)
+int get_cpu_mode(const CPUHexagonState *env)
 {
     uint32_t ssr = env->t_sreg[HEX_SREG_SSR];

diff --git a/target/hexagon/cpu_helper.h b/target/hexagon/cpu_helper.h
index ca2e13ab1d..12512efd74 100644
--- a/target/hexagon/cpu_helper.h
+++ b/target/hexagon/cpu_helper.h
@@ -15,8 +15,8 @@ void hexagon_peek_memory_range(CPUHexagonState *env, uint32_t start_addr,
                                uint32_t length, uintptr_t retaddr);
 uint32_t hexagon_get_pmu_counter(CPUHexagonState *cur_env, int index);
 void hexagon_modify_ssr(CPUHexagonState *env, uint32_t new, uint32_t old);
-int get_cpu_mode(CPUHexagonState *env);
-int get_exe_mode(CPUHexagonState *env);
+int get_cpu_mode(const CPUHexagonState *env);
+int get_exe_mode(const CPUHexagonState *env);
 void clear_wait_mode(CPUHexagonState *env);
 void hexagon_ssr_set_cause(CPUHexagonState *env, uint32_t cause);
 void hexagon_start_threads(CPUHexagonState *env, uint32_t mask);