Commit de8ffc8793 for qemu.org

commit de8ffc87930963ac621e72875d7c05bdc6581886
Author: Clément MATHIEU--DRIF <clement.mathieu--drif@bull.com>
Date:   Sat Aug 8 15:36:39 2026 +0000

    intel_iommu: Expose SMPWC when SVM is enabled

    SVM in Linux requires SMPWC. This is free in the current implementation
    as it is already in line with the expected behaviour.

    Link: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=780dfed68862
    Fixes: 952e1a6e90eb ("intel_iommu: Add a CLI option to enable SVM")
    Signed-off-by: Clement Mathieu--Drif <clement.mathieu--drif@bull.com>
    Reviewed-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
    Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
    Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
    Message-ID: <20260808153626.873965-1-clement.mathieu--drif@bull.com>

diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 91ab549dbf..350d2b7753 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -5121,7 +5121,8 @@ static void vtd_init(IntelIOMMUState *s)
     }

     if (s->svm) {
-        s->ecap |= VTD_ECAP_PRS | VTD_ECAP_PDS | VTD_ECAP_NWFS;
+        s->ecap |= VTD_ECAP_PRS | VTD_ECAP_PDS | VTD_ECAP_NWFS |
+                   VTD_ECAP_SMPWCS;
     }

     vtd_reset_caches(s);
diff --git a/hw/i386/intel_iommu_accel.c b/hw/i386/intel_iommu_accel.c
index c03435f8a2..c3677775e9 100644
--- a/hw/i386/intel_iommu_accel.c
+++ b/hw/i386/intel_iommu_accel.c
@@ -37,6 +37,12 @@ bool vtd_check_hiod_accel(IntelIOMMUState *s, VTDHostIOMMUDevice *vtd_hiod,
         return false;
     }

+    if ((s->ecap & VTD_ECAP_SMPWCS) && !(vtd->ecap_reg & VTD_ECAP_SMPWCS)) {
+        error_setg(errp,
+                   "Scalable-mode coherent walk is unsupported by host IOMMU");
+        return false;
+    }
+
     if (s->fs1gp && !(vtd->cap_reg & VTD_CAP_FS1GP)) {
         error_setg(errp,
                    "First stage 1GB large page is unsupported by host IOMMU");
diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
index 924e91cb8a..df7a0efa6e 100644
--- a/hw/i386/intel_iommu_internal.h
+++ b/hw/i386/intel_iommu_internal.h
@@ -202,6 +202,7 @@
 #define VTD_ECAP_SMTS               (1ULL << 43)
 #define VTD_ECAP_SSTS               (1ULL << 46)
 #define VTD_ECAP_FSTS               (1ULL << 47)
+#define VTD_ECAP_SMPWCS             (1ULL << 48)

 /* CAP_REG */
 /* (offset >> 4) << 24 */