Commit dfc917a1d7 for qemu.org

commit dfc917a1d7e3d45a80a7443c360eedb379261d96
Merge: fa19879df1 84dd090703
Author: Richard Henderson <richard.henderson@linaro.org>
Date:   Tue Aug 18 17:41:54 2026 -0700

    Merge tag 'pull-tcg-20260818-3' of https://gitlab.com/rth7680/qemu into staging

    accel/tcg: Allow overlapping reads in record_save
    tcg/optimize: INDEX_op_mul is commutative
    tcg/optimize: Fix s_mask computation for shifts
    tcg: Defer tb_flush when initial thread region alloc fails
    tcg: Add revbit{8,32,64} opcodes
    tcg: Add integer min/max opcodes
    disas: Updates for capstone v6

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    * tag 'pull-tcg-20260818-3' of https://gitlab.com/rth7680/qemu: (38 commits)
      target/mips: Enable disassembly via capstone
      target/m68k: Enable disassembly via capstone
      target/s390x: Update capstone disassembly to v6
      target/loongarch: Enable disassembly via capstone
      target/tricore: Enable disassembly via capstone
      target/sh4: Enable disassembly via capstone
      target/riscv: Enable disassembly via capstone
      disas/capstone: Allow for cap_insn_unit > length
      target/riscv: Improve riscv_has_ext
      tcg/aarch64: Use CTZ from FEAT_CSSC
      tcg/aarch64: Implement ctpop with FEAT_CSSC
      target/riscv64: Implement min/max with Zbb
      tcg/aarch64: Implement min/max with FEAT_CSSC
      util/cpuinfo-aarch64: Detect FEAT_CSSC
      tcg/optimize: Handle min/max opcodes
      tcg: Add integer min/max opcodes
      tests/tcg/loongarch64: Add bitrev smoke tests
      tests/tcg/loongarch64: Tidy test_bit.c
      tcg/riscv64: Implement revbit8
      util/cpuinfo-riscv: Detect Zbkb
      ...

    Signed-off-by: Richard Henderson <richard.henderson@linaro.org>