Commit ea85af3e87 for qemu.org
commit ea85af3e87453736f3d9996e333dbc4ae92b4d6d
Author: Philippe Mathieu-Daudé <philmd@linaro.org>
Date: Tue Dec 16 11:03:41 2025 +0100
hw/net/opencores: Clarify MMIO read/write handlers expect 32-bit access
The read/write handlers access array of 32-bit register by index:
277 struct OpenEthState {
..
287 uint32_t regs[REG_MAX];
..
291 };
546 static uint64_t open_eth_reg_read(void *opaque,
547 hwaddr addr, unsigned int size)
548 {
..
551 OpenEthState *s = opaque;
552 unsigned idx = addr / 4;
..
559 v = s->regs[idx];
..
563 return v;
564 }
This is a 32-bit implementation. Make that explicit in the
MemoryRegionOps structure (this doesn't change the maximum
access size, which -- being unset -- is 64-bit).
Move the structure just after the handlers to ease code review.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20251224134644.85582-3-philmd@linaro.org>
diff --git a/hw/net/opencores_eth.c b/hw/net/opencores_eth.c
index 6abeffcc9c..a25f8eccff 100644
--- a/hw/net/opencores_eth.c
+++ b/hw/net/opencores_eth.c
@@ -683,6 +683,15 @@ static void open_eth_reg_write(void *opaque,
}
}
+static const MemoryRegionOps open_eth_reg_ops = {
+ .read = open_eth_reg_read,
+ .write = open_eth_reg_write,
+ .impl = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
+};
+
static uint64_t open_eth_desc_read(void *opaque,
hwaddr addr, unsigned int size)
{
@@ -706,12 +715,6 @@ static void open_eth_desc_write(void *opaque,
open_eth_check_start_xmit(s);
}
-
-static const MemoryRegionOps open_eth_reg_ops = {
- .read = open_eth_reg_read,
- .write = open_eth_reg_write,
-};
-
static const MemoryRegionOps open_eth_desc_ops = {
.read = open_eth_desc_read,
.write = open_eth_desc_write,