Commit ea8e5d3c50 for qemu.org

commit ea8e5d3c504d38a6eb82a338dc48b9ba7b072153
Author: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Date:   Wed Aug 19 12:56:54 2026 +0200

    target/riscv: Fix sstatus update in rv128

    The sstatus register assignment was performed before the write
    mask was fully constructed, leading to an incomplete update of
    sstatus fields on the experimental rv128 target.

    Move the sstatus write after the mask completion so the full
    write mask is applied correctly.

    Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
    Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
    Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
    Reviewed-by: Chao Liu <chao.liu@processmission.com>
    Message-ID: <20260819105655.33391-2-frederic.petrot@univ-grenoble-alpes.fr>
    Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

diff --git a/target/riscv/tcg/csr.c b/target/riscv/tcg/csr.c
index ffd751caa5..9cc6297328 100644
--- a/target/riscv/tcg/csr.c
+++ b/target/riscv/tcg/csr.c
@@ -3998,7 +3998,7 @@ static RISCVException read_sstatus_i128(CPURISCVState *env, int csrno,
                                         Int128 *val)
 {
     uint64_t mask = sstatus_v1_10_mask;
-    uint64_t sstatus = env->mstatus & mask;
+    uint64_t sstatus;
     if (env->xl != MXL_RV32 || env->debugger) {
         mask |= SSTATUS64_UXL;
     }
@@ -4009,7 +4009,7 @@ static RISCVException read_sstatus_i128(CPURISCVState *env, int csrno,
     if (env_archcpu(env)->cfg.ext_zicfilp) {
         mask |= SSTATUS_SPELP;
     }
-
+    sstatus = env->mstatus & mask;
     *val = int128_make128(sstatus, add_status_sd(MXL_RV128, sstatus));
     return RISCV_EXCP_NONE;
 }