Commit ec449d0dce for qemu.org

commit ec449d0dcec26e24f37525f526d62803c9845b38
Author: Jamin Lin <jamin_lin@aspeedtech.com>
Date:   Wed Feb 25 02:12:17 2026 +0000

    hw/i3c/dw-i3c: Treat more registers as read-as-zero

    RESET_CTRL and INTR_FORCE are write-only.

    Signed-off-by: Joe Komlodi <komlodi@google.com>
    Reviewed-by: Patrick Venture <venture@google.com>
    Reviewed-by: Jamin Lin <jamin_lin@aspeedtech.com>
    Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
    Tested-by: Jithu Joseph <jithu.joseph@oss.qualcomm.com>
    Link: https://lore.kernel.org/qemu-devel/20260225021158.1586584-11-jamin_lin@aspeedtech.com
    Signed-off-by: Cédric Le Goater <clg@redhat.com>

diff --git a/hw/i3c/dw-i3c.c b/hw/i3c/dw-i3c.c
index 87c8f63da9..eeaf1125e4 100644
--- a/hw/i3c/dw-i3c.c
+++ b/hw/i3c/dw-i3c.c
@@ -342,7 +342,10 @@ static uint64_t dw_i3c_read(void *opaque, hwaddr offset, unsigned size)
     uint64_t value;

     switch (addr) {
+    /* RAZ */
     case R_COMMAND_QUEUE_PORT:
+    case R_RESET_CTRL:
+    case R_INTR_FORCE:
         value = 0;
         break;
     default: