Commit edd1c8aa89 for qemu.org
commit edd1c8aa89c455cdbc8b5b435cf019fd6597cd30
Author: Mohamed Mediouni <mohamed@unpredictable.fr>
Date: Wed Apr 22 23:42:20 2026 +0200
whpx: i386: don't increment eip on MSR access raising GPF
Signed-off-by: Mohamed Mediouni <mohamed@unpredictable.fr>
Link: https://lore.kernel.org/r/20260422214225.2242-33-mohamed@unpredictable.fr
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c
index eecc7f48ed..4bb99a8e90 100644
--- a/target/i386/whpx/whpx-all.c
+++ b/target/i386/whpx/whpx-all.c
@@ -2048,6 +2048,7 @@ int whpx_vcpu_run(CPUState *cpu)
WHV_REGISTER_NAME reg_names[3];
UINT32 reg_count;
bool is_known_msr = 0;
+ bool raises_gpf = false;
uint64_t val;
if (vcpu->exit_ctx.MsrAccess.AccessInfo.IsWrite) {
@@ -2086,6 +2087,7 @@ int whpx_vcpu_run(CPUState *cpu)
int msr_ret = cpu_set_apic_base(X86_CPU(cpu)->apic_state, val);
if (msr_ret < 0) {
x86_emul_raise_exception(&X86_CPU(cpu)->env, EXCP0D_GPF, 0);
+ raises_gpf = true;
} else {
whpx_set_reg(cpu, WHvX64RegisterApicBase, reg);
}
@@ -2105,6 +2107,7 @@ int whpx_vcpu_run(CPUState *cpu)
reg_values[1].Reg64 = val;
if (msr_ret < 0) {
x86_emul_raise_exception(&X86_CPU(cpu)->env, EXCP0D_GPF, 0);
+ raises_gpf = true;
}
} else {
bql_lock();
@@ -2112,6 +2115,7 @@ int whpx_vcpu_run(CPUState *cpu)
bql_unlock();
if (msr_ret < 0) {
x86_emul_raise_exception(&X86_CPU(cpu)->env, EXCP0D_GPF, 0);
+ raises_gpf = true;
}
}
}
@@ -2135,6 +2139,13 @@ int whpx_vcpu_run(CPUState *cpu)
if (!is_known_msr && !whpx->ignore_unknown_msr) {
x86_emul_raise_exception(&X86_CPU(cpu)->env, EXCP0D_GPF, 0);
+ raises_gpf = true;
+ }
+
+ /* When a GPF is raised, do not change Rip. */
+ if (raises_gpf) {
+ reg_values[0].Reg64 =
+ vcpu->exit_ctx.VpContext.Rip;
}
hr = whp_dispatch.WHvSetVirtualProcessorRegisters(