Commit ef25a26b7d for qemu.org
commit ef25a26b7dc29ba4b78a70d22a6a806dd4637537
Author: Richard Henderson <richard.henderson@linaro.org>
Date: Wed Aug 12 15:31:40 2026 -0700
disas/riscv: Tidy decode of mop.r.n and mop.rr.n
Merge nested if's.
Reuse operand_mop_{r,rr}_imm for zicfiss decode.
Return pointers directly.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-ID: <20260812223142.349142-51-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
diff --git a/disas/riscv.c b/disas/riscv.c
index 197eaa43b1..7ea65ba2e7 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -2555,44 +2555,33 @@ static const rv_opcode_data *decode_inst_opcode(rv_decode *dec, rv_isa isa)
case 3: op = rv_op_csrrc; break;
case 4:
if (dec->cfg && dec->cfg->ext_zimop) {
- int imm_mop5, imm_mop3, reg_num;
- if ((extract32(inst, 22, 10) & 0b1011001111)
- == 0b1000000111) {
- imm_mop5 = deposit32(deposit32(extract32(inst, 20, 2),
- 2, 2,
- extract32(inst, 26, 2)),
- 4, 1, extract32(inst, 30, 1));
- op = rv_op_mop_r;
- /* if zicfiss enabled and mop5 is shadow stack */
- if (dec->cfg->ext_zicfiss &&
- ((imm_mop5 & 0b11100) == 0b11100)) {
- /* rs1=0 means ssrdp */
- if ((inst & (0b011111 << 15)) == 0) {
- op = rv_op_ssrdp;
- }
- /* rd=0 means sspopchk */
- reg_num = (inst >> 15) & 0b011111;
- if (((inst & (0b011111 << 7)) == 0) &&
- ((reg_num == 1) || (reg_num == 5))) {
- op = rv_op_sspopchk;
+ if (((inst >> 22) & 0b1011001111) == 0b1000000111) {
+ if (dec->cfg->ext_zicfiss
+ && operand_mop_r_imm(inst) == 28) {
+ switch (operand_rs1(inst)) {
+ case 0:
+ return &rvi_opcode_data[rv_op_ssrdp];
+ case 1:
+ case 5:
+ if (operand_rd(inst) == 0) {
+ return &rvi_opcode_data[rv_op_sspopchk];
}
+ }
}
- } else if ((extract32(inst, 25, 7) & 0b1011001)
- == 0b1000001) {
- imm_mop3 = deposit32(extract32(inst, 26, 2),
- 2, 1, extract32(inst, 30, 1));
- op = rv_op_mop_rr;
- /* if zicfiss enabled and mop3 is shadow stack */
- if (dec->cfg->ext_zicfiss &&
- ((imm_mop3 & 0b111) == 0b111)) {
- /* rs1=0 and rd=0 means sspush */
- reg_num = (inst >> 20) & 0b011111;
- if (((inst & (0b011111 << 15)) == 0) &&
- ((inst & (0b011111 << 7)) == 0) &&
- ((reg_num == 1) || (reg_num == 5))) {
- op = rv_op_sspush;
- }
+ return &rvi_opcode_data[rv_op_mop_r];
+ }
+ if (((inst >> 25) & 0b1011001) == 0b1000001) {
+ if (dec->cfg->ext_zicfiss
+ && operand_mop_rr_imm(inst) == 7
+ && operand_rd(inst) == 0
+ && operand_rs1(inst) == 0) {
+ switch (operand_rs2(inst)) {
+ case 1:
+ case 5:
+ return &rvi_opcode_data[rv_op_sspush];
+ }
}
+ return &rvi_opcode_data[rv_op_mop_rr];
}
}
break;