Commit f8e830300c for qemu.org

commit f8e830300c9edeaa142fe4cc244d63770a3be4f5
Author: Zhao Liu <zhao1.liu@intel.com>
Date:   Mon Dec 15 15:37:33 2025 +0800

    i386/cpu: Add support for MOVRS in CPUID enumeration

    MOVRS is a new set of instructions introduced in the Intel platform
    Diamond Rapids, to load instructions that carry a read-shared hint.

    Functionally, MOVRS family is equivalent to existing load instructions,
    but its read-shared hint indicates the source memory location is likely
    to become read-shared by multiple processors, i.e., read in the future
    by at least one other processor before it is written (assuming it is
    ever written in the future). It could optimize the behavior of the
    caches, especially shared caches, for this data for future reads by
    multiple processors. Additionally, MOVRS family also includes a software
    prefetch instruction, PREFETCHRST2, that carries the same read-shared
    hint. [*]

    MOVRS family is enumerated by CPUID single-bit (0x7.0x1.EAX[bit 31]).
    Add its enumeration support.

    [*]: Intel Architecture Instruction Set Extensions and Future Features
         (rev.059).

    Tested-by: Xudong Hao <xudong.hao@intel.com>
    Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
    Link: https://lore.kernel.org/r/20251215073743.4055227-2-zhao1.liu@intel.com
    Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 67769200d0..817f78a0c2 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1266,7 +1266,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
             NULL, "fred", "lkgs", "wrmsrns",
             NULL, "amx-fp16", NULL, "avx-ifma",
             NULL, NULL, "lam", NULL,
-            NULL, NULL, NULL, NULL,
+            NULL, NULL, NULL, "movrs",
         },
         .cpuid = {
             .eax = 7,
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index c0bf51448e..be430a73bd 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1043,6 +1043,8 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w);
 #define CPUID_7_1_EAX_AVX_IFMA          (1U << 23)
 /* Linear Address Masking */
 #define CPUID_7_1_EAX_LAM               (1U << 26)
+/* MOVRS Instructions */
+#define CPUID_7_1_EAX_MOVRS             (1U << 31)

 /* The immediate form of MSR access instructions */
 #define CPUID_7_1_ECX_MSR_IMM           (1U << 5)