Commit fcabc76ddf for qemu.org

commit fcabc76ddfce0a8d459c31e3122994b557ad09e8
Merge: 4c4b309510 b7d87fb10d
Author: Stefan Hajnoczi <stefanha@redhat.com>
Date:   Sun May 24 07:44:52 2026 -0400

    Merge tag 'pull-riscv-to-apply-20260522' of https://github.com/alistair23/qemu into staging

    RISC-V PR for 11.1.

    * Remove spike as default machine
    * Deprecate the shakti_c machine
    * Set MISA.[C|X] based on the selected extensions
    * Update Maintainers for OpenSBI Firmware
    * Update OpenSBI to v1.8.1
    * Avoid RISCVCPU copy in PMU FDT setup
    * A collection of specification compliance improvements
    * Fix Svnapot 64KB pages
    * Handle source overlap of vector widening reduction instructions
    * Check interrupt in SiFive UART after txctrl register is written
    * Fix medeleg[11] read-only zero bit for M-mode ECALL
    * Fix tail handling for vmv.s.x and vfmv.s.f
    * Update the local AIA interrupt mask
    * Add KVM support for Zicbop and BFloat16 extensions
    * Fix the IOMMU FSC SV32 capability check
    * Avoid caching PCI device IDs in the IOMMU
    * Implement Microchip mpfs ioscb PLLs and sysreg clock dividers
    * Remove the internal CPU riscv_cpu_* arrays
    * Fix IOCOUNTINH.CY toggle detection
    * Fix the read of pmpaddr(0-63) CSRs
    * Make hpmcounterh return the upper 32-bits
    * Minor fixes and enhancements of RISC-V AIA devices
    * Re-process IOMMU command queue after clearing CMD_ILL

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    * tag 'pull-riscv-to-apply-20260522' of https://github.com/alistair23/qemu: (48 commits)
      hw/riscv: riscv-iommu: Re-process command queue after clearing CMD_ILL
      hw/intc: riscv_aplic: add trace events of APLIC read/write function
      hw/intc: riscv_imsic: Add reset API to IMSIC
      hw/intc: riscv_aplic: Add reset API to APLIC
      hw/intc: riscv_aplic: Fix level trigger IRQ in direct delivery mode
      target/riscv: Make hpmcounterh return the upper 32-bits
      hw/riscv/virt-acpi-build: Fix off-by-one error in RIMT ID mapping
      target/riscv/csr.c: fix read of pmpaddr(0-63) CSRs
      hw/riscv/riscv-iommu: Fix IOCOUNTINH.CY toggle detection
      target/riscv/cpu: remove riscv_cpu_* arrays
      target/riscv/tcg: use isa_edata_arr[] to create user props
      target/riscv: do not set defaults in cpu prop callback
      target/riscv/tcg: use cfg_offset as cpu_set_multi_ext cb opaque
      target/riscv/tcg: use isa_edata_arr[] to enable max exts
      target/riscv/kvm: use isa_edata_arr[] for unavailable props
      target/riscv/tcg: use isa_edata_arr[] in riscv_cpu_update_misa_x()
      target/riscv: remove riscv_cpu_named_features[]
      target/riscv/cpu.c: remove riscv_cpu_enable_named_feat()
      target/riscv/tcg: use only isa_edata_arr[] in cpu_cfg_ext_get_name()
      target/riscv/tcg: treat all exts equally in cpu_disable_priv_spec_isa_exts
      ...

    Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>